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019da2e539
This is the SPI client chip in the LCD displays on ESP32 WROVER-KIT and S2 Kaluga. Adapt it to allocate using DMA-able allocators and to use the new blit op conventions for update sequencing
384 lines
10 KiB
C
384 lines
10 KiB
C
/*
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* lws abstract display implementation for ili9341 on spi
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*
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* Copyright (C) 2019 - 2022 Andy Green <andy@warmcat.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* This is somewhat complicated by the platform SPI may a) need special
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* allocation for the display driver-private packed line buffers, and b) the
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* allocated memory may have 32-bit alignment and access requirements.
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*
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* The allocation is handled by having ops members in the SPI driver ops struct,
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* the alignment has to be observed in the display driver.
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*/
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#include <private-lib-core.h>
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#include <dlo/private-lib-drivers-display-dlo.h>
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enum {
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ILI9341_NOP = 0x00,
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ILI9341_SWRESET = 0x01,
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ILI9341_RDDID = 0x04,
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ILI9341_RDDST = 0x09,
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ILI9341_SLPIN = 0x10,
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ILI9341_SLPOUT = 0x11,
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ILI9341_PTLON = 0x12,
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ILI9341_NORON = 0x13,
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ILI9341_RDMODE = 0x0a,
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ILI9341_RDMADCTL = 0x0b,
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ILI9341_RDPIXFMT = 0x0c,
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ILI9341_RDIMGFMT = 0x0d,
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ILI9341_RDSELFDIAG = 0x0f,
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ILI9341_INVOFF = 0x20,
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ILI9341_INVON = 0x21,
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ILI9341_GAMMASET = 0x26,
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ILI9341_DISPOFF = 0x28,
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ILI9341_DISPON = 0x29,
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ILI9341_CASET = 0x2a,
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ILI9341_PASET = 0x2b,
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ILI9341_RAMWR = 0x2c,
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ILI9341_RAMRD = 0x2e,
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ILI9341_PTLAR = 0x30,
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ILI9341_VSCRDEF = 0x33,
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ILI9341_MADCTL = 0x36,
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ILI9341_VSCRSADD = 0x37,
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ILI9341_PIXFMT = 0x3a,
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ILI9341_FRMCTR1 = 0xb1,
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ILI9341_FRMCTR2 = 0xb2,
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ILI9341_FRMCTR3 = 0xb3,
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ILI9341_INVCTR = 0xb4,
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ILI9341_DFUNCTR = 0xb6,
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ILI9341_PWCTR1 = 0xc0,
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ILI9341_PWCTR2 = 0xc1,
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ILI9341_PWCTR3 = 0xc2,
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ILI9341_PWCTR4 = 0xc3,
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ILI9341_PWCTR5 = 0xc4,
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ILI9341_VMCTR1 = 0xc5,
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ILI9341_VMCTR2 = 0xc7,
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ILI9341_FACPUMPRAT = 0xcb,
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ILI9341_FACPWCTRB = 0xcf,
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ILI9341_RDID1 = 0xda,
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ILI9341_RDID2 = 0xdb,
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ILI9341_RDID3 = 0xdc,
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ILI9341_RDID4 = 0xdd,
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ILI9341_GMCTRP1 = 0xe0,
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ILI9341_GMCTRN1 = 0xe1,
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ILI9341_FACPWCTRA = 0xe8,
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ILI9341_FACPWCTR1 = 0xea,
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ILI9341_FACDRTIMCTRA = 0xed,
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ILI9341_FACSETGAMMACRV = 0xf2,
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ILI9341_FACDRTIMCTR = 0xf7,
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};
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typedef struct lws_display_ili9341_spi_state {
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struct lws_display_state *lds;
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uint32_t *line[2];
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lws_surface_error_t *u[2];
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lws_sorted_usec_list_t sul;
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} lws_display_ili9341_spi_state_t;
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#define lds_to_disp(_lds) (const lws_display_ili9341_t *)_lds->disp;
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#define lds_to_priv(_lds) (lws_display_ili9341_spi_state_t *)_lds->priv;
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#define pack_native_pixel(_line, _x, _c) { \
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if (!(_x & 1)) \
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*_line = htons(_c); \
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else \
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{ *_line = (*_line) | (htons(_c) << 16); _line++; } }
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static const uint8_t ili9341_320x240_init[] = {
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/*
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* This provides 70Hz 320x240 at RGB565, we assume im[3:0] is 1110
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* which is 4-bit SPI
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*/
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3, ILI9341_FACPWCTRB, 0x00, 0x83, 0x30,
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4, ILI9341_FACDRTIMCTRA, 0x64, 0x03, 0x12, 0x81,
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3, ILI9341_FACPWCTRA, 0x85, 0x01, 0x79,
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5, ILI9341_FACPUMPRAT, 0x39, 0x2c, 0x00, 0x34, 0x02,
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1, ILI9341_FACDRTIMCTR, 0x20,
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2, ILI9341_FACPWCTR1, 0x00, 0x00,
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1, ILI9341_PWCTR1, 0x26,
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1, ILI9341_PWCTR2, 0x11,
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2, ILI9341_VMCTR1, 0x35, 0x3e,
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1, ILI9341_VMCTR2, 0xbe,
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1, ILI9341_MADCTL, 0x28,
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1, ILI9341_VSCRSADD, 0x00,
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1, ILI9341_PIXFMT, 0x55,
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2, ILI9341_FRMCTR1, 0x00, 0x1b,
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1, ILI9341_FACSETGAMMACRV, 0x00,
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1, ILI9341_GAMMASET, 0x01,
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15, ILI9341_GMCTRP1, 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e,
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0xf1, 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09,
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0x00,
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15, ILI9341_GMCTRN1, 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31,
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0xc1, 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36,
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0x0f,
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4, ILI9341_DFUNCTR, 0x0a, 0x82, 0x27, 0x00,
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0, ILI9341_SLPOUT
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}, ili9341_320x240_dispon[] = {
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0, ILI9341_DISPON
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}, ili9341_320x240_sleep_in[] = {
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0, ILI9341_SLPIN
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}, ili9341_320x240_sleep_out[] = {
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0, ILI9341_SLPOUT
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};
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int
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lws_display_ili9341_spi_init(lws_display_state_t *lds)
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{
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const lws_display_ili9341_t *disp = lds_to_disp(lds);
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lws_display_ili9341_spi_state_t *priv;
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priv = lws_zalloc(sizeof(*priv), __func__);
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if (!priv)
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return 1;
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priv->lds = lds;
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lds->priv = priv;
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/* hardware nRESET */
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if (disp->gpio) {
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disp->gpio->mode(disp->reset_gpio, LWSGGPIO_FL_WRITE |
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LWSGGPIO_FL_PULLUP);
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disp->gpio->set(disp->reset_gpio, 0);
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lws_msleep(1);
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disp->gpio->set(disp->reset_gpio, 1);
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lws_msleep(1);
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}
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lws_spi_table_issue(disp->spi, 0, ili9341_320x240_init,
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LWS_ARRAY_SIZE(ili9341_320x240_init));
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lws_msleep(5);
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lws_spi_table_issue(disp->spi, 0, ili9341_320x240_dispon,
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LWS_ARRAY_SIZE(ili9341_320x240_dispon));
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if (disp->spi->in_flight)
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while (disp->spi->in_flight(disp->spi))
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;
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if (disp->cb)
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disp->cb(priv->lds, 1);
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return 0;
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}
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/* backlight handled by PWM */
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int
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lws_display_ili9341_spi_brightness(lws_display_state_t *lds, uint8_t b)
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{
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return 0;
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}
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int
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lws_display_ili9341_spi_blit(lws_display_state_t *lds, const uint8_t *src,
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lws_box_t *box, lws_dll2_owner_t *ids)
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{
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lws_display_ili9341_spi_state_t *priv = lds_to_priv(lds);
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const lws_display_ili9341_t *disp = lds_to_disp(lds);
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const lws_surface_info_t *ic = &lds->disp->ic;
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lws_greyscale_error_t *gedl_this, *gedl_next;
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lws_colour_error_t *edl_this, *edl_next;
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int bytes_pl = ic->wh_px[0].whole * 2;
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static DMA_ATTR uint32_t buf[5];
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lws_display_list_coord_t h, y;
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lws_display_colour_t c;
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lws_spi_desc_t desc;
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const uint8_t *pc;
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uint32_t *lo;
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int n, m;
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if (!priv->line[0]) {
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if (disp->spi->alloc_dma)
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priv->line[0] = disp->spi->alloc_dma(disp->spi,
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bytes_pl * 2);
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else
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priv->line[0] = lws_malloc(bytes_pl * 2, __func__);
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if (!priv->line[0]) {
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lwsl_err("%s: failed to alloc %u\n", __func__,
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(unsigned int)bytes_pl * 2);
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return 1;
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}
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priv->line[1] = (uint32_t *)((uint8_t *)priv->line[0] + bytes_pl);
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if (lws_display_alloc_diffusion(ic, priv->u)) {
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if (disp->spi->free_dma)
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disp->spi->free_dma(disp->spi,
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(void **)&priv->line[0]);
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else
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lws_free_set_NULL(priv->line[0]);
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lwsl_err("%s: OOM\n", __func__);
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return 1;
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}
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}
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pc = src;
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lo = priv->line[box->y.whole & 1];
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memset(&desc, 0, sizeof(desc));
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desc.count_cmd = 1;
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desc.src = (uint8_t *)&buf[4];
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/*
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* Blit a line at a time
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*/
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h = box->h.whole;
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y = box->y.whole;
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if (h > 1) {
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buf[4] = ILI9341_CASET;
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desc.data = (uint8_t *)&buf[0];
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desc.flags = 0;
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buf[0] = ((box->w.whole & 0xff) << 24) | ((box->w.whole >> 8) << 16) | (box->x.whole) | (box->x.whole);
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desc.count_write = 4;
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disp->spi->queue(disp->spi, &desc);
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buf[4] = ILI9341_PASET;
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// buf[0] = (((y + 1) & 0xff) << 24) | (((y + 1) >> 8) << 16) | ((y & 0xff) << 8) | (y >> 8);
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buf[0] = (((box->h.whole) & 0xff) << 24) | (((box->h.whole) >> 8) << 16) | ((y & 0xff) << 8) | (y >> 8);
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disp->spi->queue(disp->spi, &desc);
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buf[4] = ILI9341_RAMWR;
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/* priv->line is already allocated for DMA */
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desc.flags = LWS_SPI_FLAG_DMA_BOUNCE_NOT_NEEDED | LWS_SPI_FLAG_DATA_CONTINUE;
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desc.count_write = 0;
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disp->spi->queue(disp->spi, &desc);
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return 0;
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}
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if (h) {
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edl_this = (lws_colour_error_t *)priv->u[(box->y.whole & 1) ^ 1];
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edl_next = (lws_colour_error_t *)priv->u[box->y.whole & 1];
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gedl_this = (lws_greyscale_error_t *)edl_this;
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gedl_next = (lws_greyscale_error_t *)edl_next;
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if (!pc) {
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for (n = 0; n < ic->wh_px[0].whole; n++)
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pack_native_pixel(lo, n, 0xffff);
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goto go;
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}
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if (ic->greyscale)
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for (n = 0; n < ic->wh_px[0].whole; n++) {
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c = (pc[0] << 16) | (pc[0] << 8) | pc[0];
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m = lws_display_palettize_grey(ic, ic->palette,
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ic->palette_depth, c, &gedl_this[n]);
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pack_native_pixel(lo, n, m);
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dist_err_floyd_steinberg_grey(n, ic->wh_px[0].whole,
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gedl_this, gedl_next);
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pc++;
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}
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else
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for (n = 0; n < ic->wh_px[0].whole; n++) {
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c = (pc[2] << 16) | (pc[1] << 8) | pc[0];
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m = lws_display_palettize_col(ic, ic->palette,
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ic->palette_depth, c, &edl_this[n]);
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pack_native_pixel(lo, n, m);
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dist_err_floyd_steinberg_col(n, ic->wh_px[0].whole,
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edl_this, edl_next);
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pc += 3;
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}
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go:
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desc.flags = LWS_SPI_FLAG_DMA_BOUNCE_NOT_NEEDED;
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if (y + 1 != ic->wh_px[1].whole)
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desc.flags |= LWS_SPI_FLAG_DATA_CONTINUE;
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desc.data = (uint8_t *)priv->line[box->y.whole & 1];
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desc.count_write = bytes_pl;
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desc.count_cmd = 0;
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if (disp->spi->queue(disp->spi, &desc)) {
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lwsl_err("%s: failed to queue\n", __func__);
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}
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src += bytes_pl;
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y++;
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return 0;
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}
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if (!box->h.whole) {
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if (disp->spi->in_flight)
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while (disp->spi->in_flight(disp->spi))
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;
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if (disp->spi->free_dma)
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disp->spi->free_dma(disp->spi, (void **)&priv->line[0]);
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else
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lws_free_set_NULL(priv->line[0]);
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lws_free_set_NULL(priv->u[0]);
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if (disp->cb)
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disp->cb(priv->lds, 2);
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}
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return 0;
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}
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int
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lws_display_ili9341_spi_power(lws_display_state_t *lds, int state)
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{
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const lws_display_ili9341_t *disp = lds_to_disp(lds);
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if (state)
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lws_spi_table_issue(disp->spi, 0, ili9341_320x240_sleep_out,
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LWS_ARRAY_SIZE(ili9341_320x240_sleep_out));
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else
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lws_spi_table_issue(disp->spi, 0, ili9341_320x240_sleep_in,
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LWS_ARRAY_SIZE(ili9341_320x240_sleep_in));
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/* we're not going to do anything useful for 5ms after this */
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return 0;
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}
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