mirror of
https://libwebsockets.org/repo/libwebsockets
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e3743d47b4
This provides an alternative esp32-specific SPI driver with ops that can be swapped in place of the gpio bitbang one. The pinmux info and lws gpio driver and other data in the spi bitbang struct are used as-is by the DMA one. New ops are provided which are able to allocate and free DMA-able memory so the device drivers can prepare directly usable buffers. Bounce through to DMA-able buffers is also transparently supported.
131 lines
3.6 KiB
C
131 lines
3.6 KiB
C
/*
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* SPI bitbang implementation using generic gpio
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*
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* Copyright (C) 2019 - 2020 Andy Green <andy@warmcat.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <libwebsockets.h>
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int
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lws_bb_spi_init(const lws_spi_ops_t *octx)
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{
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lws_bb_spi_t *ctx = (lws_bb_spi_t *)octx;
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int n;
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for (n = 0; n < LWS_SPI_BB_MAX_CH; n++) {
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if (ctx->flags & (1 << n))
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ctx->gpio->mode(ctx->ncs[n], LWSGGPIO_FL_WRITE);
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if (ctx->flags & (1 << (n + 4)))
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ctx->gpio->mode(ctx->ncmd[n], LWSGGPIO_FL_WRITE);
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}
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ctx->gpio->mode(ctx->clk, LWSGGPIO_FL_WRITE |
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((octx->bus_mode & LWSSPIMODE_CPOL) ?
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0 : LWSGGPIO_FL_START_LOW));
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ctx->gpio->mode(ctx->mosi, LWSGGPIO_FL_WRITE | LWSGGPIO_FL_START_LOW);
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ctx->gpio->mode(ctx->miso, LWSGGPIO_FL_READ | LWSGGPIO_FL_PULLUP);
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return 0;
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}
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/* if active, prepare DnC before this and call separately for Cmd / Data */
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static void
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lws_bb_spi_write(lws_bb_spi_t *ctx, const uint8_t *buf, size_t len)
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{
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uint8_t u, inv = !!(ctx->bb_ops.bus_mode & LWSSPIMODE_CPOL);
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while (len--) {
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int n;
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u = *buf++;
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for (n = 0; n < 4; n++) {
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ctx->gpio->set(ctx->clk, inv);
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ctx->gpio->set(ctx->mosi, !!(u & 0x80));
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ctx->gpio->set(ctx->clk, !inv);
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ctx->gpio->set(ctx->clk, inv);
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ctx->gpio->set(ctx->mosi, !!(u & 0x40));
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ctx->gpio->set(ctx->clk, !inv);
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u <<= 2;
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}
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}
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ctx->gpio->set(ctx->clk, 0 ^ inv);
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}
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static void
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lws_bb_spi_read(lws_bb_spi_t *ctx, uint8_t *buf, size_t len)
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{
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uint8_t u = 0;
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uint8_t inv = !!(ctx->bb_ops.bus_mode & LWSSPIMODE_CPOL);
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while (len--) {
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int n;
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for (n = 0; n < 8; n++) {
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ctx->gpio->set(ctx->clk, inv);
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u = (u << 1) | !!ctx->gpio->read(ctx->miso);
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ctx->gpio->set(ctx->mosi, !!(u & 0x80));
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ctx->gpio->set(ctx->clk, !inv);
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}
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*buf++ = u;
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}
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ctx->gpio->set(ctx->clk, 0 ^ inv);
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}
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int
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lws_bb_spi_queue(const lws_spi_ops_t *octx, const lws_spi_desc_t *desc)
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{
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lws_bb_spi_t *ctx = (lws_bb_spi_t *)octx;
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const uint8_t *src = desc->src;
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/* clock to idle */
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ctx->gpio->set(ctx->clk, 0 ^ !!(octx->bus_mode & LWSSPIMODE_CPOL));
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/* enable nCS */
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ctx->gpio->set(ctx->ncs[desc->channel], 0);
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if (desc->count_cmd) {
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ctx->gpio->set(ctx->ncmd[desc->channel], 0);
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lws_bb_spi_write(ctx, src, desc->count_cmd);
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ctx->gpio->set(ctx->ncmd[desc->channel], 1);
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src += desc->count_cmd;
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}
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if (desc->count_write)
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lws_bb_spi_write(ctx, desc->data, desc->count_write);
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if (desc->count_read)
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lws_bb_spi_read(ctx, desc->dest, desc->count_read);
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if (desc->flags & LWS_SPI_FLAG_DATA_CONTINUE)
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return 0;
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/* disable nCS */
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ctx->gpio->set(ctx->ncs[desc->channel], 1);
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/* clock to idle */
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ctx->gpio->set(ctx->clk, 0 ^ !!(octx->bus_mode & LWSSPIMODE_CPOL));
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return 0;
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}
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